100,000 cycles are specified by the chip manufacturer, but not guaranteed.
Since the data memory is structured as a ring buffer anyway, the same blocks are only written once per run. Such a run can last from 1 time per day to months, depending on the recording density.
The counter readings are saved in a flash area every 1/4 hour. However, 5 blocks are kept ready as fail-safe and are automatically switched on in case of an error. So far, however, we have not had such a case within 5 years.